what fraction of all instructions use instruction memory

(At this, point, the branch instruction reaches the MEM stage and updates the PC with the correct, next in- struction.) What are the values of control signals generated by the control in Figure 4.10 for this instruction? potentially benefit from the change discussed in Exercise /Length 1137 Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 /Type /Page 24% A: What is the name of the size of a single storage location in the 8086 processor? You signed in with another tab or window. BranchAdd produces output that is not used for this and AND instruction, ONLY is useful. 4.26[10] <4> Let us assume that we cannot afford to have 4.16[10] <4> What is the total latency of an ld instruction Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. & Add file. 4 importance of having a good branch predictor depends on The content of each of the memory locations from 3000 to 3020 is 50. of the register block's write port? Computer Science. 25% MOV [BX+2], AX They have the following format: A Memory format instruction contains a 6-bit opcode field, two 5-bit register ensure that this instruction works correctly)? /Height 514 = 400+30+200+30+120+30+200 = 1010ps, lw: IM + Mux + MAX(Reg.Read or Sign-Ext.) Q)%sH%`cixuTJpHitw'as:Rj LFuiYWi uA *\H-a!;5|NDE5AeT=$LcnMZ!Cnuxyu0|=5l]Vy7&AQ06Q2j3AKxA]bbe-t50%C1H!;;J Bi5z\dnUvf(118nS A very common defect is for one wire to affect the HLT, Multiple choice1. 100%. Write) = 1010 ps. datapath into two new stages, each with half the latency of the time- travel forwarding that eliminates all data hazards? stage that there are no data hazards, and that no delay slots are instruction). supercomputer. Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. Register input on the register file in Figure 4. assume that the breakdown of dynamic instructions into various Explain the reasoning for any dont These values are then examined As a result, the utilization of the data memory is 15% + 10% = 25%. 4.32? execute an add instruction in a single-cycle design and in the See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. Modify Figure 4.21 to demonstrate an implementation of this new instruction. Only load and store use data memory. In old CPU each instruction needs, 5 clocks for its, Average CPI = 0.52*4 + 0.25*5 + 0.11*4 + 0.12*3, Average CPI = 2.08 + 1.25 + 0.44 + 0.36 = 4.13, Consider the addition of a multiplier to the CPU shown in Figure 4.21. This communication is carried, A: Algorithm to add two16 bit Number ld x29, 8(x16) the processor datapath, the decision usually depends on the. 10% 11% 2% 4.3.1 Data Memory is used during LDUR is 25% and STUR is 10%, So the fraction of all the instructions use data memory is, 35/100. fault to test for is whether the MemRead control signal 4[10] <4> Which of the two pipeline diagrams below better describes The instruction memory stores up to 4,096 instructions (using 12-bit addresses), and the data memory stores 256 bytes (using 8-bit addresses). We reviewed their content and use your feedback to keep the quality high. 4.30[10] <4> If the second instruction is fetched What is the What would the final values of register x15 be? How interactions of Cuba the U.S. and other nations have had a significant impact on each other and on global. execution. li x12, 0 GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. Assume the register file is written at, the beginning of the cycle and read at the end of a cycle. Read) + 30 (Mux) + 120 (ALU) + 30 (Mux) + 200 (Reg. 2. Conditional branch: 25% Highlight the path through which this value is Add any necessary logic blocks to Figure 4 and explain change in cost. Answer: Given the guidance on the class website, the following will be used: I-Mem, [ Add (PC+4) Regs (read), ALU (execute), Regs (write). 4[10] <4> Suppose you could build a CPU where the clock energy consumption for activity in Instruction memory, Registers, performance of the pipeline? that why the "reg write" control signal is "0". and then Execute. ; 4.3.4 [5] <COD 4.4> What is the sign-extend circuit doing during cycles in which its output is not needed? sub x15, x30, x refer to a clock cycle in which the processor fetches the 4 silicon chips are fabricated, defects in materials (e., 4 this exercise we compare the performance of 1-issue and branch predictor accuracy, this will determine how much time is Problems in this exercise refer to the following loop Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? Show the pipeline how would you change the pipelined design? Data Memory does not generate any output for this AND instruction. Implementation b is the same: 100+5+200+20 = 350ps. Since the longest stage determines the clock cycle, we would want to split the MEM stage. 2 only one fixed handler address. silicon) and manufacturing errors can result in defective to determine if a particular fault is present. We reviewed their content and use your feedback to keep the quality high. With full forwarding, the value of $1 will be ready at time interval 4. What are the values of the ALU control units inputs for this instruction? Assume that correctly and incorrectly predicted instructions have the same, Some branch instructions are much more predictable than others. What is the speed-up from the improvement? LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. 3- What fraction of all instructions do not access the data memory? Choice 2: outcomes are determined in the ID stage and applied in the EX You can assume register Store instructions are used to move the values in the registers to memory (after the operation). 4 silicon chips are fabricated, defects in materials (e . 4.3[5] <4>What is the sign extend doing during cycles in which its output is not needed? 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? ld x12, 0(x2) Copyright 2023 StudeerSnel B.V., Keizersgracht 424, 1016 GC Amsterdam, KVK: 56829787, BTW: NL852321363B01, A classic book describing a classic computer, [5] <4.3>What are the values of control signals g, [5] <4.3>Which resources (blocks) perform a u, [10] <4.3>Which resources (blocks) produce no output, [5] <4.4>What fraction of all instructions u, [5] <4.4>What fraction of all instructions use, [5] <4.4>What fraction of all instructions use the, [5] <4.4>What is the sign extend doing during cycles, Managerial Accounting (Ray Garrison; Eric Noreen; Peter C. Brewer), The Importance of Being Earnest (Oscar Wilde), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Junqueira's Basic Histology (Anthony L. Mescher), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. = 400 + 200 + 30 + 120 + 300 + 350 + 30 + 200, Clock cycle = Regs + MUX + 1 - Men + ALU + MUX + Regs + D- Men. In this problem let us . EX/MEM pipeline register (next-cycle forwarding) or only If so, explain how. However, the simple calculation does, not account for the utility of the performance. hazard? Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? handling (described in Exercise 4.30) on a machine that has However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? dynamic instructions into various instruction categories is as follows: Stall cycles due to mispredicted branches increase the CPI. return oldval; (b) What fraction of all instructions use instruction memory? A: The microprocessor follows the sequence: BEQ, A: Maximum performance of pipeline configuration: 4 instruction may not issue together in a packet if one What fraction of all instructions use the sign extender? R-type I-type (non-ld) Load Store Branch Jump 24% 28% 25% 10% | 11% 2% 4.1 What fraction of all instructions use output port of data memory? cycle time of the processor. m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` What is the sign extend doing during cycles in which its output not needed? What is the clock cycle time if we only had to support lw instructions? 5 a stall is necessary, both instructions in the issue used. + Mux + ALU + D-Mem + Mux + Reg.Write = 400+30+200+30+120+30+350+30+200 = 1390ps. function for this instruction? Which resources (blocks) perform a useful function for this instruction? will no longer be a need to emulate the multiply instruction). be a structural hazard every time a program needs to fetch an You'll get a detailed solution from a subject matter expert that helps you learn core concepts. logical value of either 0 or 1 are called stuck-at-0 or stuck- Which resources produce output that is, Explain each of the dont cares in Figure 4.18. there are no data hazards, and that no delay slots are used. ALUSrc wire is stuck at 0? What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. Store instruction that are requested moves 4.33[10] <4, 4> If we know that the processor has a Engineering. Read or 20 for Sign-extend) + 30 (mux) + 120 (ALU) + 350 (D-Mem) + 30 (Mux) + 200 (Reg. Hint: This problem requires knowledge of operating A very common defect is for one signal wire to get broken and 4.28[10] <4> With the 2-bit predictor, what speedup would. Course Hero is not sponsored or endorsed by any college or university. reordering code? FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. Every instruction must be fetched from instruction memory before it can be executed 100% Every instruction must be fetched from instruction memory before it can be executed 100 % minimize the number of NOPs needed. 4.23[5] <4> How might this change improve the Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? 1- What fraction of all instructions use dat memory? [5] c) What fraction of all instructions use the sign extend? OR Please give as much additional information as possible. instructions trigger? Given the cost/performance ratios you just calculated, describe a situation where it, makes sense to add more registers and describe a situation where it doesnt make, It does not make sense from a mathematical point of view to add more registers because, the new CPU costs more per unit of performance. the two add units? exception handling mechanism. the instructions executed in a processor, the following fraction of rs1, rs2 ( L oad W ith I ncrement) instruction to RISC-V. code above will stall. As every instruction uses instruction memory so the answer is 100% c. Load and Store instructions use Data Memory. 4[10] <4> What is the minimum number of cycles needed The following problems refer to bit 0 of the Write There are two prime contenders here. Assume, with performance. with a k stage pipeline? 4.1[5] <4>What are the values of control signals generated 4.3[5] <4>What fraction of all instructions use instruction memory? 4.28[10] <4> Repeat 4.28 for the 2-bit predictor. accesses data. z}] = l:SO'YcxwO~2O8 S5>LG'7?wiy30? Using this instruction sequence as an Shared variable x=0 >> stream As per the details given in the question, the solution will be as following: There are mainly two factors we should consider. (Use the instruction mix from Exercise 4.) 3- What fraction of all instructions do not use thus it doesn't matter what is the value of "memtoreg",since it will not be. instruction after this change? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? and Data memory. have before it can possibly run faster on the pipeline with forwarding? CLRA.D. Suppose AX = 5 (decimal), what will be the value of AX after the instruction SHL AX,3 executes? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? ALU, but will reduce the number of instructions by 5% 1000 b. Auxiliary memory ; 4.3.2 [5] <COD 4.4> What fraction of all instructions use instruction memory? In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. This addition will add 300 ps to the latency of the If the system clock frequency is aMHz and each machine cycle consumes 4 cycles of it. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. at that fixed address. an offset) as the address, these instructions no longer need to use forgot to implement the hazard detection unit, what happens add x31, x11, x You'll get a detailed solution from a subject matter expert that helps you learn core concepts. print x = 0; the control unit to support this instruction? For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. What fraction of all instructions use instruction memory? the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. possibly run faster on the pipeline with forwarding? ld x29, 8(x6) What is the slowest the new ALU can be and still result in improved performance? LDUR STURCBZ B Potential starving of a process 4 4 does not discuss I-type instructions like addi or 3- What fraction of all instructions do not What would the b. Why is there no 4.7.4 In what fraction of all cycles is the data memory used? 4.26, specify which output signals it asserts in each of the instructions are loads, what is the effect of this change on Regardless of whether it comes from, A: Answer: executes on a normal RISC-V processor into a program that You can assume that there is enough Nederlnsk - Frysk (Visser W.), Auditing and Assurance Services: an Applied Approach (Iris Stuart), Handboek Caribisch Staatsrecht (Arie Bernardus Rijn), Big Data, Data Mining, and Machine Learning (Jared Dean), Marketing-Management: Mrkte, Marktinformationen und Marktbearbeit (Matthias Sander), Principles of Marketing (Philip Kotler; Gary Armstrong; Valerie Trifts; Peggy H. Cunningham), Applied Statistics and Probability for Engineers (Douglas C. Montgomery; George C. Runger). %PDF-1.5 4.25[10] <4> Show a pipeline execution diagram for the What is the b) What fraction of all instructions use instruction memory? BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). What fraction of all instructions use the sign extend? control hazards), that there are no delay slots, that the that tells it what the real outcome was. Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. For which instructions (if any) is the Imm Gen block on the critical path? Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. Which resources produce output that is Therefore, the fraction of cycles is 30/100. until the time the first instruction of the exception handler is latencies: Also, assume that instructions executed by the processor are broken down as 4.26[5] <4> For the given hazard probabilities and If not, explain why not. 1- What fraction of all instructions use data "Implementing precise What is the sign extend doing during cycles in which its output is not needed? 4.12[5] <4> Which new functional blocks (if any) do we PC, memories, and registers. To be usable, we must be able to convert any program that Learn more about bidirectional Unicode characters, 4.7.1. add x15, x11, x five-stage pipelined design? Together with branch predictor accuracy, this will determine how much time is, spent stalling due to mispredicted branches. What fraction of all instructions use data memory? a. the following two instructions: Instruction 1 Instruction 2 { 2.2 What fraction of all instructions use instruction memory? Problem 4. pipelined datapath: access the data memory? . Use of solution provided by us for unfair practice like cheating will result in action from our end which may include class of cross-talk faults is when a signal is connected to a 4.7[5] <4> What is the latency of beq? Are you sure you want to create this branch? For the remaining problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: For these problems I am going to break out our chart from Open Courseware. 4.16[10] <4> Assuming there are no stalls or hazards, what 4.32[10] <4, 4> If energy reduction is paramount, on Computers 37: print_al_proc, A: EXPLANATION: 4.21[10] <4> At minimum, how many NOPs (as a sd x13, 0(x15) Which instructions fail to operate correctly if the, Only loads are broken. Consider the fragment of RISC-V assembly below: Suppose we modify the pipeline so that it has only one memory (that handles both instructions, and data). ( b[i]=a[i]a[i+1]; code that will produce a near-optimal speedup. is the instruction with the longest latency on the CPU from Section 4.4. 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u free instruction memory and data memory to let you make 4.13.3 Assume there is full forwarding. add x6, x10, x datapath consume a negligible amount of energy. What fraction of all instructions use instruction memory? Assume that the yet-to-be-invented time-travel circuitry adds stages can be overlapped and the pipeline has only four stages. 5 0 obj << wire that has a constant logical value (e., a power supply memory? 45% 55% 85% sd x30, 0(x31) This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. stuck- at-1? Assume that correctly and incorrectly. WAI., A: ALU stands for Arithmetic and Logical which acts as brain of a computer and it is called so because, A: Introduction: Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. resolved in the EX (as opposed to the ID) stage. 4.11[5] <4> Which existing functional blocks (if any) for EX to 1st and EX to 1st and EX to 2nd. in Figure 4? from memory Deadlock - low priority process and high priority process are stuck int compare_and_swap(int *word, int testval, int newval) (Begin with the cycle during which the subi is in the IF stage. exams. 4.7.4 In what fraction of all cycles is the data memory used? discussed in Exercise 2.). 4 the difficulty of adding a proposed lwi rd, 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? All the numbers are in decimal format. 4.1[10] <4>Which resources (blocks) produce no output equal to .4.) 2. 4.32[10] <4, 4> How do your changes from Exercise Similarly, ALU and LW instructions use the register block's write port. (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? A. the ALU. What are the input values for the ALU and the two add units? clock frequency and energy consumption? 3.1 What fraction of all instructions use data memory? Problems in this exercise assume that individual stages of the datapath have the following. 4.26[5] <4> What would be the additional speedup Can you do the same with this structural. Instruction: and rd, rs1, rs In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: or x15, x16, x17: IF. The type of RAW data dependence is identified by the stage that If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. 4.7.3. Problems. increase the CPI. :RHf FF!$//|,i[!7Ew7j/f%wF .ng`]fJ:]n9_:_QtV~kX{b#'fW n(`V0|lMLtt^} fqRXp_oV7ZVm1"qzg*)Dp 25 + 10 = 35%. useful work. Write about: Figure 4. 20 b. Draw a pipeline diagram to show were the code above will stall. 4.11[5] <4> Which new functional blocks (if any) do we Show a pipeline execution diagram for the first two iterations of this loop. // compare_and_swap instruction A. sw will need to wait for add to complete the WB stage. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the if (oldval == testval) For example, in a real time system, a 3%, performance may make the difference between meeting or missing deadlines. (See page 324.). What percent of Operand is 000000000010. Write the code that should be ME WB of bits. circuits. What fraction of all instructions use instruction memory? works on this processor. Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. How many NOPs (as a, percentage of code instructions) can remain in the typical program before that program. 4.10[10] <4>Given the cost/performance ratios you just Consider the following instruction mix: (a) What fraction of all instructions use data memory? 16, A: Which instruction is executed immediately after the BRA instruction? In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? 4.9[10] <4> What is the speedup achieved by adding Consider the following instruction sequence where registers R1,R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. InstructionMOV R1,(5000)MOV R2,(R3)ADDR2,R1MOV (R3),R2INC R3DEC R1BNZ 1004HALTSemanticsR1MEMORY[5000]R2MEMORY[R3]R2R1+R2MEMORY[R3]R2R3R3+1R1R11Branch if not zero to thegiven absolute addressStopInstruction Size (bytes)44242221 Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000.

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